library verilog;
use verilog.vl_types.all;
entity Initial_Permutation is
    port(
        Input_Text      : in     vl_logic_vector(64 downto 1);
        Initial_Permutation_Select: in     vl_logic;
        Initial_Permutation_Output: out    vl_logic_vector(64 downto 1);
        Initial_Permutation_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Initial_Permutation;
